A sense amplifier is a circuit that reads data from a memory cell of a memory array. The sense amplifier senses low voltage signals from a bitline representing a data bit (“1” or “0”) stored in the memory cell, and amplifies the low voltage signals to full CMOS-level voltage signals for digital post processing.
A reading operation by a sense amplifier is triggered by a memory address change or a dedicated read start and has two phases—a precharge phase and a sense phase. During the precharge phase the bitline capacitance is charged to precharge potential VDDpre. In the subsequent sense phase, the bitline is discharged by the memory cell current towards voltage source VSS (e.g., ground). The sense amplifier acts as a voltage comparator comparing a sense voltage (i.e., reference voltage) with the voltage on the bitline. When a low resistive cell is accessed (data bit ‘0’), the bitline is discharged faster as compared with a bitline discharge corresponding to a high resistive cell (data bit ‘1’). The sense amplifier's digital output signal changes to a logic “0” when the bitline voltage becomes less than the sense voltage.
A sense amplifier's power consumption should be as low as possible in order to achieve targets for ultra-low power applications. There are features of sense amplifiers of previous approaches that detract from this goal.
For instance, a sense amplifier is continuously biased from a global voltage supply, thereby consuming static and dynamic power. Further, the sense amplifier may be biased during the sense phase by voltage supply VDD. Also, the bitline is typically precharged from a regulated supply VDDpre, thereby requiring additional circuitry and current.
Even further, good power supply rejection ratios typically require voltage regulation for the bitline voltage or the sense amplifier itself, increasing power consumption further. In addition, the maximum bitline voltage is limited by the voltage headroom required by the voltage regulation.